CMOS imager with selectively silicided gates

ABSTRACT

The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the CMOS imager.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a divisional of application Ser. No.11/078,709, filed Mar. 14, 2005, which is a continuation of applicationSer. No. 10/617,706, filed Jul. 14, 2003, not U.S. Pat. No. 6,930,337,which is a continuation of application Ser. No. 09/777,890, filed Feb.7, 2001, now U.S. Pat. No. 6,611,013, which is a divisional ofapplication Ser. No. 09/374,990, filed Aug. 16, 1999, now U.S. Pat. No.6,333,205, the disclosures of which are incorporated herein by referencein their entireties.

FIELD OF THE INVENTION

The invention relates generally to improved semiconductor imagingdevices and in particular to an imaging device which can be fabricatedusing a standard CMOS process. Particularly, the invention relates to amethod for providing a silicide coating over the transistor gates usedin a CMOS imager to improve the operating speed of the transistors.

DISCUSSION OF RELATED ART

There are a number of different types of semiconductor-based imagers,including charge coupled devices (CCDs), photodiode arrays, chargeinjection devices and hybrid focal plane arrays. CCDs are often employedfor image acquisition and enjoy a number of advantages which makes itthe incumbent technology, particularly for small size imagingapplications. CCDs are also capable of large formats with small pixelsize and they employ low noise charge domain processing techniques.However, CCD imagers also suffer from a number of disadvantages. Forexample, they are susceptible to radiation damage, they exhibitdestructive read out over time, they require good light shielding toavoid image smear and they have a high power dissipation for largearrays. Additionally, while offering high performance, CCD arrays aredifficult to integrate with CMOS processing in part due to a differentprocessing technology and to their high capacitances, complicating theintegration of on-chip drive and signal processing electronics with theCCD array. While there has been some attempts to integrate on-chipsignal processing with the CCD array, these attempts have not beenentirely successful. CCDs also must transfer an image by line chargetransfers from pixel to pixel, requiring that the entire array be readout into a memory before individual pixels or groups of pixels can beaccessed and processed. This takes time. CCDs may also suffer fromincomplete charge transfer from pixel to pixel during charge transferwhich also results in image smear.

Because of the inherent limitations in CCD technology, there is aninterest in CMOS imagers for possible use as low cost imaging devices. Afully compatible CMOS sensor technology enabling a higher level ofintegration of an image array with associated processing circuits wouldbe beneficial to many digital applications such as, for example, incameras, scanners, machine vision systems, vehicle navigation systems,video telephones, computer input devices, surveillance systems, autofocus systems, star trackers, motion detection systems, imagestabilization systems and data compression systems for high-definitiontelevision.

The advantages of CMOS imagers over CCD imagers are that CMOS imagershave a low voltage operation and low power consumption; CMOS imagers arecompatible with integrated on-chip electronics (control logic andtiming, image processing, and signal conditioning such as A/Dconversion); CMOS imagers allow random access to the image data; andCMOS imagers have lower fabrication costs as compared with theconventional CCD since standard CMOS processing techniques can be used.Additionally, low power consumption is achieved for CMOS imagers becauseonly one row of pixels at a time needs to be active during the readoutand there is no charge transfer (and associated switching) from pixel topixel during image acquisition. On-chip integration of electronics isparticularly advantageous because of the potential to perform manysignal conditioning functions in the digital domain (versus analogsignal processing) as well as to achieve a reduction in system size andcost.

A CMOS imager circuit includes a focal plane array of pixel cells, eachone of the cells including either a photogate, photoconductor or aphotodiode overlying a substrate for accumulating photo-generated chargein the underlying portion of the substrate. A readout circuit isconnected to each pixel cell and includes at least an output fieldeffect transistor formed in the substrate and a charge transfer sectionformed on the substrate adjacent the photogate, photoconductor orphotodiode having a sensing node, typically a floating diffusion node,connected to the gate of an output transistor. The imager may include atleast one electronic device such as a transistor for transferring chargefrom the underlying portion of the substrate to the floating diffusionnode and one device, also typically a transistor, for resetting the nodeto a predetermined charge level prior to charge transference.

In a CMOS imager, the active elements of a pixel cell perform thenecessary functions of: (1) photon to charge conversion; (2)accumulation of image charge; (3) transfer of charge to the floatingdiffusion node accompanied by charge amplification; (4) resetting thefloating diffusion node to a known state before the transfer of chargeto it; (5) selection of a pixel for readout; and (6) output andamplification of a signal representing pixel charge. Photo charge may beamplified when it moves from the initial charge accumulation region tothe floating diffusion node. The charge at the floating diffusion nodeis typically converted to a pixel output voltage by a source followeroutput transistor. The photosensitive element of a CMOS imager pixel istypically either a depleted p-n junction photodiode or a field induceddepletion region beneath a photogate, or a photoconductor. Forphotodiodes, image lag can be eliminated by completely depleting thephotodiode upon readout.

CMOS imagers of the type discussed above are generally known asdiscussed, for example, in Nixon et al., “256×256 CMOS Active PixelSensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol.31(12) pp. 2046-2050, 1996; Mendis et al, “CMOS Active Pixel ImageSensors,” IEEE Transactions on Electron Devices, Vol. 41(3) pp. 452-453,1994 as well as U.S. Pat. No. 5,708,263 and U.S. Pat. No. 5,471,515,which are herein incorporated by reference.

To provide context for the invention, an exemplary CMOS imaging circuitis described below with reference to FIG. 1. The circuit describedbelow, for example, includes a photogate for accumulatingphoto-generated charge in an underlying portion of the substrate. Itshould be understood that the CMOS imager may include a photodiode orother image to charge converting device, in lieu of a photogate, as theinitial accumulator for photo-generated charge.

Reference is now made to FIG. 1 which shows a simplified circuit for apixel of an exemplary CMOS imager using a photogate and having a pixelphotodetector circuit 14 and a readout circuit 60. It should beunderstood that while FIG. 1 shows the circuitry for operation of asingle pixel, that in practical use there will be an M×N array of pixelsarranged in rows and columns with the pixels of the array accessed usingrow and column select circuitry, as described in more detail below.

The photodetector circuit 14 is shown in part as a cross-sectional viewof a semiconductor substrate 16 typically a p-type silicon, having asurface well of p-type material 20. An optional layer 18 of p-typematerial may be used if desired, but is not required. Substrate 16 maybe formed of, for example, Si, SiGe, Ge, and GaAs. Typically the entiresubstrate 16 is p-type doped silicon substrate and may contain a surfacep-well 20 (with layer 18 omitted), but many other options are possible,such as, for example p on p− substrates, p on p+ substrates, p-wells inn-type substrates or the like. The terms wafer or substrate used in thedescription includes any semiconductor-based structure having an exposedsurface in which to form the circuit structure used in the invention.Wafer and substrate are to be understood as including,silicon-on-insulator (SOI) technology, silicon-on-sapphire (SOS)technology, doped and undoped semiconductors, epitaxial layers ofsilicon supported by a base semiconductor foundation, and othersemiconductor structures. Furthermore, when reference is made to a waferor substrate in the following description, previous process steps mayhave been utilized to form regions/junctions in the base semiconductorstructure or foundation.

An insulating layer 22 such as, for example, silicon dioxide is formedon the upper surface of p-well 20. The p-type layer may be a p-wellformed in substrate 16. A photogate 24 thin enough to pass radiantenergy or of a material which passes radiant energy is formed on theinsulating layer 22. The photogate 24 receives an applied control signalPG which causes the initial accumulation of pixel charges in n+ region26. The n+ type region 26, adjacent one side of photogate 24, is formedin the upper surface of p-well 20. A transfer gate 28 is formed oninsulating layer 22 between n+ type region 26 and a second n+ typeregion 30 formed in p-well 20. The n+ regions 26 and 30 and transfergate 28 form a charge transfer transistor 29 which is controlled by atransfer signal TX. The n+ region 30 is typically called a floatingdiffusion region. It is also a node for passing charge accumulatedthereat to the gate of an amplifying transistor, such as source followertransistor 36 described below. A reset gate 32 is also formed oninsulating layer 22 adjacent and between n+ type region 30 and anothern+ region 34 which is also formed in p-well 20. The reset gate 32 and n+regions 30 and 34 form a reset transistor 31 which is controlled by areset signal RST. The n+ type region 34 is coupled to voltage sourceVDD, e.g., 5 volts. The transfer and reset transistors 29, 31 aren-channel transistors as described in this implementation of a CMOSimager circuit in a p-well. It should be understood that it is possibleto implement a CMOS imager in an n-well in which case each of thetransistors would be p-channel transistors. It should also be noted thatwhile FIG. 1 shows the use of a transfer gate 28 and associatedtransistor 29, this structure provides advantages, but is not required.

Photodetector circuit 14 also includes two additional n-channeltransistors, source follower transistor 36 and row select transistor 38.Transistors 36, 38 are coupled in series, source to drain, with thesource of transistor 36 also coupled over lead 40 to voltage source VDDand the drain of transistor 38 coupled to a lead 42. The drain of rowselect transistor 38 is connected via conductor 42 to the drains ofsimilar row select transistors for other pixels in a given pixel row. Aload transistor 39 is also coupled between the drain of transistor 38and a voltage source VSS, e.g. 0 volts. Transistor 39 is kept on by asignal VLN applied to its gate.

The imager includes a readout circuit 60 which includes a signal sampleand hold (S/H) circuit including a S/H n-channel field effect transistor62 and a signal storage capacitor 64 connected to the source followertransistor 36 through row transistor 38. The other side of the capacitor64 is connected to a source voltage VSS. The upper side of the capacitor64 is also connected to the gate of a p-channel output transistor 66.The drain of the output transistor 66 is connected through a columnselect transistor 68 to a signal sample output node VOUTS and through aload transistor 70 to the voltage supply VDD. A signal called “signalsample and hold” (SHS) briefly turns on the S/H transistor 62 after thecharge accumulated beneath the photogate electrode 24 has beentransferred to the floating diffusion node 30 and from there to thesource follower transistor 36 and through row select transistor 38 toline 42, so that the capacitor 64 stores a voltage representing theamount of charge previously accumulated beneath the photogate electrode24.

The readout circuit 60 also includes a reset sample and hold (S/H)circuit including a S/H transistor 72 and a signal storage capacitor 74connected through the S/H transistor 72 and through the row selecttransistor 38 to the source of the source follower transistor 36. Theother side of the capacitor 74 is connected to the source voltage VSS.The upper side of the capacitor 74 is also connected to the gate of ap-channel output transistor 76. The drain of the output transistor 76 isconnected through a p-channel column select transistor 78 to a resetsample output node VOUTR and through a load transistor 80 to the supplyvoltage VDD. A signal called “reset sample and hold” (SHR) briefly turnson the S/H transistor 72 immediately after the reset signal RST hascaused reset transistor 31 to turn on and reset the potential of thefloating diffusion node 30, so that the capacitor 74 stores the voltageto which the floating diffusion node 30 has been reset.

The readout circuit 60 provides correlated sampling of the potential ofthe floating diffusion node 30, first of the reset charge applied tonode 30 by reset transistor 31 and then of the stored charge from thephotogate 24. The two samplings of the diffusion node 30 charges producerespective output voltages VOUTR and VOUTS of the readout circuit 60.These voltages are then subtracted (VOUTS-VOUTR) by subtractor 82 toprovide an output signal terminal 81 which is an image signalindependent of pixel to pixel variations caused by fabricationvariations in the reset voltage transistor 31 which might cause pixel topixel variations in the output signal.

FIG. 2 illustrates a block diagram for a CMOS imager having a pixelarray 200 with each pixel cell being constructed in the manner shown byelement 14 of FIG. 1. Pixel array 200 comprises a plurality of pixelsarranged in a predetermined number of columns and rows. The pixels ofeach row in array 200 are all turned on at the same time by a row selectline, e.g., line 86, and the pixels of each column are selectivelyoutput by a column select line, e.g., line 42. A plurality of rows andcolumn lines are provided for the entire array 200. The row lines areselectively activated by the row driver 210 in response to row addressdecoder 220 and the column select lines are selectively activated by thecolumn driver 260 in response to column address decoder 270. Thus, a rowand column address is provided for each pixel. The CMOS imager isoperated by the control circuit 250 which controls address decoders 220,270 for selecting the appropriate row and column lines for pixelreadout, and row and column driver circuitry 210, 260 which applydriving voltage to the drive transistors of the selected row and columnlines.

FIG. 3 shows a simplified timing diagram for the signals used totransfer charge out of photodetector circuit 14 of the FIG. 1 CMOSimager. The photogate signal PG is nominally set to 5V and pulsed from5V to 0V during integration. The reset signal RST is nominally set at2.5V. As can be seen from the figure, the process is begun at time to bybriefly pulsing reset voltage RST to 5V. The RST voltage, which isapplied to the gate 32 of reset transistor 31, causes transistor 31 toturn on and the floating diffusion node 30 to charge to the VDD voltagepresent at n+ region 34 (less the voltage drop Vth of transistor 31).This resets the floating diffusion node 30 to a predetermined voltage(VDD-Vth). The charge on floating diffusion node 30 is applied to thegate of the source follower transistor 36 to control the current passingthrough transistor 38, which has been turned on by a row select (ROW)signal, and load transistor 39. This current is translated into avoltage on line 42 which is next sampled by providing a SHR signal tothe S/H transistor 72 which charges capacitor 74 with the sourcefollower transistor output voltage on line 42 representing the resetcharge present at floating diffusion node 30. The PG signal is nextpulsed to 0 volts, causing charge to be collected in n+ region 26. Atransfer gate voltage TX, similar to the reset pulse RST, is thenapplied to transfer gate 28 of transistor 29 to cause the charge in n+region 26 to transfer to floating diffusion node 30. It should beunderstood that for the case of a photogate, the transfer gate voltageTX may be pulsed or held to a fixed DC potential. For the implementationof a photodiode with a transfer gate, the transfer gate voltage TX mustbe pulsed. The new output voltage on line 42 generated by sourcefollower transistor 36 current is then sampled onto capacitor 64 byenabling the sample and hold switch 62 by signal SHS. The column selectsignal is next applied to transistors 68 and 70 and the respectivecharges stored in capacitors 64 and 74 are subtracted in subtractor 82to provide a pixel output signal at terminal 81. It should also be notedthat CMOS imagers may dispense with the transfer gate 28 and associatedtransistor 29, or retain these structures while biasing the transfertransistor 29 to an always “on” state.

The operation of the charge collection of the CMOS imager is known inthe art and is described in several publications such as Mendis et al.,“Progress in CMOS Active Pixel Image Sensors,” SPIE Vol. 2172, pp. 19-291994; Mendis et al., “CMOS Active Pixel Image Sensors for HighlyIntegrated Imaging Systems,” IEEE Journal of Solid State Circuits, Vol.32(2), 1997; and Eric R, Fossum, “CMOS Image Sensors: Electronic Cameraon a Chip,” IEDM Vol. 95 pages 17-25 (1995) as well as otherpublications. These references are incorporated herein by reference.

In the prior art, the desire to incorporate a silicide over the gatestack to improve speed was hampered by the undesirable effect thesilicide layer had on the photogate. If the photogate is covered by asilicide layer, the collection of charge is inhibited by the blocking oflight by the silicide layer. It is for this reason that photogate typedevices have not been able to use a silicide gate stack. Since the sizeof the pixel electrical signal is very small due to the collection ofphotons in the photo array, the signal to noise ratio of the pixelshould be as high as possible within a pixel. Accordingly, all possiblecharge should be collected by the photocollection device.

SUMMARY OF THE INVENTION

The present invention provides an imaging device formed as a CMOSintegrated circuit using a standard CMOS process. The invention relatesto a method for providing a more conductive layer, such as a silicide ora barrier/metal layer, incorporated into the transistor gates of a CMOSimager to improve the speed of the transistor gates, but selectivelyremoving the silicide or barrier/metal from a photogate to preventblockage of the photogate.

The above and other advantages and features of the invention will bemore clearly understood from the following detailed description which isprovided in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a representative circuit of a CMOS imager.

FIG. 2 is a block diagram of a CMOS active pixel sensor chip.

FIG. 3 is a representative timing diagram for the CMOS imager.

FIG. 4 illustrates a partially cut away side view of a portion of asemiconductor CMOS imager wafer in an interim stage of processing.

FIG. 5 illustrates a partially cut away side view of a portion of asemiconductor CMOS imager wafer subsequent to FIG. 4.

FIG. 6 illustrates a partially cut away side view of a portion of asemiconductor CMOS imager wafer subsequent to FIG. 5.

FIG. 7 illustrates a partially cut away side view of a portion of asemiconductor CMOS imager wafer in an interim stage of processingaccording to a further embodiment of the present invention.

FIG. 8 illustrates a partially cut away side view of a portion of asemiconductor CMOS imager wafer subsequent to FIG. 7.

FIG. 9 illustrates a partially cut away side view of a portion of asemiconductor CMOS imager wafer subsequent to FIG. 8.

FIG. 10 illustrates a partially cut away side view of a portion of asemiconductor CMOS imager wafer subsequent to FIG. 9.

FIG. 11 illustrates a partially cut away side view of a portion of asemiconductor CMOS imager wafer subsequent to FIG. 10.

FIG. 12 illustrates a partially cut away side view of a portion of asemiconductor CMOS imager wafer in an interim stage of processingaccording to a second embodiment of the present invention.

FIG. 13 illustrates a partially cut away side view of a portion of asemiconductor CMOS imager wafer subsequent to FIG. 12.

FIG. 14 illustrates a partially cut away side view of a portion of asemiconductor CMOS imager wafer subsequent to FIG. 13.

FIG. 15 illustrates a partially cut away side view of a portion of asemiconductor CMOS imager wafer in an interim stage of processingaccording to a third embodiment of the present invention.

FIG. 16 illustrates a partially cut away side view of a portion of asemiconductor CMOS imager wafer subsequent to FIG. 15.

FIG. 17 illustrates a partially cut away side view of a portion of asemiconductor CMOS imager wafer subsequent to FIG. 16.

FIG. 18 is an illustration of a computer system having a CMOS imageraccording to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following detailed description, reference is made to theaccompanying drawings which form a part hereof, and in which is shown byway of illustration specific embodiments in which the invention may bepracticed. It should be understood that like reference numeralsrepresent like elements. These embodiments are described in sufficientdetail to enable those skilled in the art to practice the invention, andit is to be understood that other embodiments may be utilized, and thatstructural, logical and electrical changes may be made without departingfrom the spirit and scope of the present invention.

The terms “wafer” and “substrate” are to be understood as includingsilicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology,doped and undoped semiconductors, epitaxial layers of silicon supportedby a base semiconductor foundation, and other semiconductor structures.Furthermore, when reference is made to a “wafer” or “substrate” in thefollowing description, previous process steps may have been utilized toform regions or junctions in the base semiconductor structure orfoundation. In addition, the semiconductor need not be silicon-based,but could be based on silicon-germanium, germanium, or gallium arsenide.

The term “pixel” refers to a picture element unit cell containing aphotosensor and transistors for converting electromagnetic radiation toan electrical signal. For purposes of illustration, a representativepixel is illustrated in the figures and description herein, andtypically fabrication of all pixels in an imager will proceedsimultaneously in a similar fashion. The following detailed descriptionis, therefore, not to be taken in a limiting sense, and the scope of thepresent invention is defined by the appended claims.

Reference is now made to FIG. 4. This figure shows a partially cut awayside view of a portion of a semiconductor CMOS imager wafer in aninterim stage of processing according to a first aspect of the presentinvention. The imager includes a substrate 310 preferably doped to afirst conductivity type. For exemplary purposes, it is assumed that thesubstrate 310 is a well doped to a p-type conductivity, i.e., a p-well.Substrate 310 has an n-doped region 316 therein for photocollection. Aninsulating layer 315 is formed over the substrate 310. The insulatinglayer is preferably a silicon dioxide grown on the substrate 310 byconventional means such as thermal oxidation of silicon. The substrate310 has field oxide regions 341 formed using the Local Oxidation ofSilicon (LOCOS) process to surround and isolate the cells which may beformed by thermal oxidation. While the invention is described withreference to LOCOS formed field oxide regions 341, it should beunderstood that the field oxide regions may be formed with shallowtrench isolation (STI).

A photogate 340, a transfer gate 350 and a reset gate 360 have beenfabricated over the insulating layer 315. The gates 340, 350, 360include a doped polysilicon layer 320 covered by a more conductive layersuch as a barrier/metal layer or silicide layer 325 or refractory metalsilicide or barrier metal, if desired, according to conventionalmethods. Preferably the silicide is a tungsten, titanium, tantalum,molybdenum or cobalt silicide. The barrier metal may be those such astitanium nitride, tungsten nitride or the like. Preferably the barriermetal is formed of a TiN/W, WN_(x)/W or WN_(x).

The doped polysilicon layers 320 may be formed by conventional methods,such as chemical vapor deposition (CVD). Conductive layer 325 oftitanium, tantalum, cobalt or tungsten is then deposited using achemical vapor deposition (CVD), sputtering or a physical vapordeposition (PVD) of the silicide or a CVD or PVD deposition of the metalfollowed by a thermal step to cause the metal to react with theunderlying polysilicon to form the metal silicide. The wafer is thenannealed at approximately 600° C. to about 800° C. for approximately 30seconds in a nitrogen environment to react with a portion of thepolysilicon layer 320 to form conductive layer 325. The excess metal isthen removed to arrive at the structure shown in FIG. 4. Preferably theconductive layer 325 is formed by depositing WSi_(X) over the dopedpolysilicon layers 320. The WSi_(X) may be deposited onto the dopedpolysilicon layers 320 by conventional methods such as CVD. Photoresistis then used to define features 340, 350, 360 and the silicide andpolysilicon layers and etched, preferably using a dry etch that stops inthe underlying gate oxide. The resist is stripped and the wafer is shownin FIG. 4.

The substrate is then patterned, exposing the photogate, and theconductive layer 325 is removed from the photogate 340 by a wet or dryetch to arrive at the device as shown in FIG. 5. The conductive layer325 remains over both the transfer gate 350 and the reset gate 360 afterthe pattern mask is removed. This process improves the speed of thefabricated transistor gates by depositing a conductive layer on thesegates while the process removes the conductive layer from the photogate340 to prevent blockage of the photo-generated charge. Thus, thetransistor gates 350, 360 have the desired speed due to the presence ofthe silicide but the area of the photogate 340 is not shielded by thesilicide.

Spacers 324 are formed along the sides of the gate stacks 340, 350, 360as shown in FIG. 6. The spacers 324 may be formed of TEOS(tetraethyloxysilicate) or silicon nitride using conventional depositionand etch back technique. A resist and mask (not shown) are used toshield areas of the substrate 310 that are not to be doped. The dopedregions 312, 314, 318 are then formed in the substrate 310. The dopedregions 312, 314, 318 are doped to a second conductivity type, which forexemplary purposes will be considered to be n-type. The doping level ofthe doped regions 312, 314, 318 may be different but for processsimplicity could all be heavily n+ doped with arsenic, antimony ofphosphorous at an implant dose of from about 1×10¹⁵ ions/cm² to about1×10¹⁶ ions/cm². There may be other implants (not shown) to settransistor threshold voltages, provide short channel punch-throughprotection, provide improved field isolation, etc. as is known in theart.

For the pixel cell of the first embodiment, the photosensor cell isessentially complete at this stage, and conventional processing methodsmay then be used to form contacts and wiring to connect gate lines andother connections in the pixel cell. For example, the entire surface maythen be covered with a passivation layer of, e.g., silicon dioxide,BPSG, PSG, BSG or the like which is CMP planarized and etched to providecontact holes, which are then metallized to provide contacts to thephotogate, reset gate, and transfer gate. Conventional multiple layersof conductors and insulators may also be used to interconnect thestructures in the manner shown in FIG. 1.

Reference is now made to FIG. 7. This figure shows a partially cut awayside view of a portion of a semiconductor CMOS imager wafer in aninterim stage of processing according to a second embodiment of thepresent invention. The imager includes a p-well substrate 310 havingn-doped region 316 therein for photocollection. An insulating layer 315is formed over the substrate 310. The insulating layer is preferably asilicon dioxide grown on the substrate 310 by conventional means such asthermal oxidation of silicon. The substrate 310 has field oxide regions341 formed to surround and isolate the cells which may be formed bythermal oxidation of silicon using the LOCOS process. While theinvention is described with reference to field oxide regions 341, itshould be understood that the field oxide regions may be replaced withshallow trench isolation (STI). A doped polysilicon layer 320 may beformed by conventional methods, such as chemical vapor deposition (CVD)over the insulating layer 315. A photogate insulator 342 grown ordeposited over layer 320 and is patterned over the polysilicon layer 320above n-doped region 316 as shown in FIG. 7.

Referring now to FIG. 8, a metal layer 326 of titanium or cobalt is thendeposited using CVD or PVD technique, preferably sputtering. The waferis then annealed at approximately 600° C. to about 800° C. forapproximately 30 seconds in a nitrogen environment to react with aportion of the polysilicon layer 320 to form conductive layer 325. Theunreacted metal layer 326 over insulating regions such as 342 is thenremoved to arrive at the structure shown in FIG. 9.

A resist and mask (not shown) is then applied to the substrate 310 andthe wafer is patterned and the silicide and polysilicon layers areetched to form transfer gate 350 and reset gate 360 over the substrate310 as shown in FIG. 10. While the photogate insulation 342 does nothave to be removed, it may be removed if desired. FIG. 10 shows theinsulator 342 left in place. The gates 350 and 360 include the dopedpolysilicon layer 320 covered by conductive layer 325. The conductivelayer 325 is selectively removed from the substrate 310 as shown in FIG.10 by a wet or dry etch or other chemical and/or mechanical methods inregions not protected by the patterned photoresist. The conductive layer325 remains over both the transfer gate 350 and the reset gate 360 afterthe pattern mask is removed. This process improves the speed of thetransistor gates by depositing a silicide layer on these gates while theprocess selectively prevents silicide from forming over the photogateregion 340 by using a patterned insulating layer 342 to prevent blockageof the photo-generated charge. Thus, the transistor gates 350, 360 havethe desired speed due to the presence of the silicide but the area ofthe photogate 340 is not shielded by the silicide.

Spacers 324 are formed along the sides of the gate stacks 340, 350, 360as shown in FIG. 11. The spacers 324 may be formed of any insulator suchas oxide or nitride using conventional deposition and anisotropic etchback technique. A resist and mask (not shown) is further used to shieldareas of the substrate 310 that are not to be doped. The doped regions312, 314, 318 are then formed in the substrate 310. The doped regions312, 314, 318 are doped to a second conductivity type, which forexemplary purposes will be considered to be n-type. The doping level ofthe doped regions 312 may vary but preferably are heavily n+ doped witharsenic, antimony of phosphorous at a dopant concentration level of fromabout 1×10¹⁵ ions/cm² to about 1×10¹⁶ ions/cm². Separate maskingphotoresist layers may be used to implant regions 312, 314, 318 todiffering dopant concentrations or a single mask may be used to implantthem all the same concentration.

For the pixel cell of the second embodiment, the photosensor cell isessentially complete at this stage, and conventional processing methodsmay then be used to form contacts and wiring to connect gate lines andother connections in the pixel cell. For example, the entire surface maythen be covered with a passivation layer of, e.g., silicon dioxide,BPSG, PSG, BSG or the like which is CMP planarized and etched to providecontact holes, which are then metallized to provide contacts to thephotogate, reset gate, and transfer gate. Conventional multiple layersof conductors and insulators may also be used to interconnect thestructures in the manner shown in FIG. 1.

Reference is now made to FIG. 12. This figure shows a partially cut awayside view of a portion of a semiconductor CMOS imager wafer in aninterim stage of processing according to a second embodiment of thepresent invention. The imager includes a substrate 310 preferably dopedto a first conductivity type. For exemplary purposes, it is assumed thatthe substrate 310 is a well doped to a p-type conductivity, i.e., ap-well. Substrate 310 has an n-doped region 316 therein forphotocollection. An insulating layer 315 is formed over the substrate310. The insulating layer is preferably a silicon dioxide grown on thesubstrate 310 by conventional means such as thermal oxidation ofsilicon. The substrate 310 has field oxide regions 341 formed using theLOCOS process to surround and isolate the cells which may be formed bythermal oxidation. While the invention is described with reference toLOCOS formed field oxide regions 341, it should be understood that thefield oxide regions may be formed using replaced with shallow trenchisolation (STI).

A photogate 340, a transfer gate 350 and a reset gate 360 have beenfabricated over the insulating layer 315. The gates 340, 350, 360include a doped polysilicon layer 320 covered by a more conductive layersuch as a barrier/metal layer or silicide layer 325. Preferably thesilicide is a tungsten, titanium, tantalum, molybdenum or cobaltsilicide. The barrier metal may be those such as titanium nitride,tungsten nitride or the like. Preferably the barrier metal is formed ofa TiN/W, WN_(x)/W or WN_(x). The doped polysilicon layers 320 may beformed by conventional methods as described above. Conductive layer 325of titanium, tantalum, cobalt or tungsten is then deposited using achemical vapor deposition (CVD) or a physical vapor deposition (PVD) ofthe silicide or a CVD or PVD deposition of the metal followed by athermal step to cause the metal to react with the underlying polysiliconto form the metal silicide. The wafer is then annealed at approximately600° C. to about 800° C. for approximately 30 seconds in a nitrogenenvironment to react with a portion of the polysilicon layer 320 to formconductive layer 325. The excess metal is then removed. Preferably theconductive layer 325 is formed by depositing WSi_(X) over the dopedpolysilicon layers 320. The WSi_(X) may be deposited onto the dopedpolysilicon layers 320 by conventional methods such as CVD. Aphotoresist layer 351 is formed and patterned over photogate 340.

The conductive layer 325 is removed from the photogate 340 by a wet ordry etch to arrive at the device as shown in FIG. 13. The conductivelayer ring 325 remaining after removal of conductive layer 325 overphotogate 340 allows a light shield to be aligned over the array whileallowing light to pass to the photogate 340.

Spacers 324 are formed along the sides of the gate stacks 340, 350, 360and the conductive layer ring 325 remaining after etching over thephotogate 340 as shown in FIG. 14. The spacers 324 may be formed of anyinsulator such as oxide or nitride using conventional deposition andanisotropic etch back technique. A resist and mask (not shown) isfurther used to shield areas of the substrate 310 that are not to bedoped. The doped regions 312, 314, 318 are then formed in the substrate310. The doped regions 312, 314, 318 are doped to a second conductivitytype, which for exemplary purposes will be considered to be n-type. Thedoping level of the doped regions 312 may vary but preferably areheavily n+ doped with arsenic, antimony of phosphorous at a dopantconcentration level of from about 1×10¹⁵ ions/cm² to about 1×10¹⁶ions/cm². Separate masking photoresist layers may be used to implantregions 312, 314, 318 to differing dopant concentrations or a singlemask may be used to implant them all the same concentration.

For the pixel cell of the third embodiment, the photosensor cell isessentially complete at this stage, and conventional processing methodsmay then be used to form contacts and wiring to connect gate lines andother connections in the pixel cell. For example, the entire surface maythen be covered with a passivation layer of, e.g., silicon dioxide,BPSG, PSG, BSG or the like which is CMP planarized and etched to providecontact holes, which are then metallized to provide contacts to thephotogate, reset gate, and transfer gate. Conventional multiple layersof conductors and insulators may also be used to interconnect thestructures in the manner shown in FIG. 1.

Reference is now made to FIG. 15. This figure shows a partially cut awayside view of a portion of a semiconductor CMOS imager wafer in aninterim stage of processing according to a third embodiment of thepresent invention. The imager includes a substrate 310 preferably dopedto a first conductivity type. For exemplary purposes, it is assumed thatthe substrate 310 is a well doped to a p-type conductivity, i.e., ap-well. Substrate 310 has an n-doped region 316 therein forphotocollection. An insulating layer 315 is formed over the substrate310. The insulating layer is preferably a silicon dioxide grown on thesubstrate 310 by conventional means such as thermal oxidation ofsilicon. The substrate 310 has field oxide regions 341 formed using theLOCOS process to surround and isolate the cells which may be formed bythermal oxidation. While the invention is described with reference toLOCOS formed field oxide regions 341, it should be understood that thefield oxide regions may be formed using replaced with shallow trenchisolation (STI).

A photogate 340, a transfer gate 350 and a reset gate 360 have beenfabricated over the insulating layer 315. The gates 340, 350, 360include a doped polysilicon layer 320 covered by a more conductive layersuch as a barrier/metal layer or silicide layer 325. Preferably thesilicide is a tungsten, titanium, tantalum, molybdenum or cobaltsilicide. The barrier metal may be those such as titanium nitride,tungsten nitride or the like. Preferably the barrier metal is formed ofa TiN/W, WN_(x)/W or WN_(x). The doped polysilicon layers 320 may beformed by conventional methods as described above. Conductive layer 325of titanium, tantalum, cobalt or tungsten is then deposited using achemical vapor deposition (CVD) or a physical vapor deposition (PVD) ofthe silicide or a CVD or PVD deposition of the metal followed by athermal step to cause the metal to react with the underlying polysiliconto form the metal silicide. The wafer is then annealed at approximately600° C. to about 800° C. for approximately 30 seconds in a nitrogenenvironment to react with a portion of the polysilicon layer 320 to formconductive layer 325. The excess metal is then removed. Preferably theconductive layer 325 is formed by depositing WSi_(X) over the dopedpolysilicon layers 320. The WSi_(X) may be deposited onto the dopedpolysilicon layers 320 by conventional methods such as CVD.

Reference is made to FIG. 16. Spacers 324 are formed along the sides ofthe gate stacks 340, 350, 360 and the conductive layer ring 325remaining after etching over the photogate 340, transfer gate 350 andreset gate 360. The spacers 324 may be formed of any insulator such asoxide or nitride using conventional deposition and anisotropic etch backtechnique. A resist and mask (not shown) is further used to shield areasof the substrate 310 that are not to be doped. The doped regions 312,314, 318 are then formed in the substrate 310. The doped regions 312,314, 318 are doped to a second conductivity type, which for exemplarypurposes will be considered to be n-type. The doping level of the dopedregions 312 may vary but preferably are heavily n+ doped with arsenic,antimony of phosphorous at a dopant concentration level of from about1×10¹⁵ ions/cm² to about 1×10¹⁶ ions/cm². Separate masking photoresistlayers may be used to implant regions 312, 314, 318 to differing dopantconcentrations or a single mask may be used to implant them all the sameconcentration. A resist and mask (not shown) is used to form insulatinglayer 370 over substrate 310. The insulating layer 370 is formed suchthat the insulating layer aligns with the remaining conductive layer 325as shown in FIG. 16.

The insulating layer 370 may be formed of any type of insulatingmaterial, such as an oxide or nitride. A light shield 374 is thendeposited over insulating layer 374. The light shield layer may beformed of any conventionally known light blocking material. The wafer isthen patterned with resist to clear resist over the photogate 340 andwherever a subsequent contact is desired. The light shield 374,insulating layer 370 and conductor 325 are all etched sequentially witha single resist patterning. The resist is stripped and the wafer is asshown in FIG. 16.

A translucent or transparent insulating layer 380 is then deposited overthe substrate. The substrate is optionally planarized using CMP orspin-on-glass (SOG). Contact holes 382 are formed in insulating layer380 to arrive at the structure shown in FIG. 17. Insulating layer 380may be formed of, for example, silicon dioxide, BPSG, PSG, BSG, SOG orthe like which is CMP planarized and etched to provide contact holes382, which are then metallized to provide contacts to the photogate 340,reset gate 350, and transfer gate 360. Conventional multiple layers ofconductors and insulators may also be used to interconnect thestructures in the manner shown in FIG. 1.

A typical processor based system which includes a CMOS imager deviceaccording to the present invention is illustrated generally at 400 inFIG. 18. A processor based system is exemplary of a system havingdigital circuits which could include CMOS imager devices. Without beinglimiting, such a system could include a computer system, camera system,scanner, machine vision, vehicle navigation, video phone, surveillancesystem, auto focus system, star tracker system, motion detection system,image stabilization system and data compression system forhigh-definition television, all of which can utilize the presentinvention.

A processor system, such as a computer system, for example generallycomprises a central processing unit (CPU) 444 that communicates with aninput/output (I/O) device 446 over a bus 452. The CMOS imager 442 alsocommunicates with the system over bus 452. The computer system 400 alsoincludes random access memory (RAM) 448, and, in the case of a computersystem may include peripheral devices such as a floppy disk drive 454and a compact disk (CD) ROM drive 456 which also communicate with CPU444 over the bus 452. CMOS imager 442 is preferably constructed as anintegrated circuit as previously described with respect to FIGS. 4-17.

The above description and accompanying drawings are only illustrative ofpreferred embodiments which can achieve the features and advantages ofthe present invention. For example, the CMOS imager array can be formedon a single chip together with the logic or the logic and array may beformed on separate IC chips. It is not intended that the invention belimited to the embodiments shown and described in detail herein.Accordingly, the invention is not limited by the forgoing descriptions,but is only limited by the scope of the following claims.

1-86. (canceled)
 87. A method of forming an imager, comprising: formingan array of pixel cells comprising: forming a plurality of gates;forming a silicide on at least a portion of said plurality of gates; andremoving said silicide from at least a portion of at least one of saidplurality of gates.
 88. The method of claim 87, wherein forming saidplurality of gates includes forming a photogate and said removing actcomprises removing said silicide from at least a portion of saidphotogate.
 89. The method of claim 88, wherein said removing actcomprises retaining at least a portion of said silicide on saidphotogate.
 90. The method of claim 88, wherein said removing actcomprises retaining at least a portion of said silicide on at least oneof said plurality of gates.
 91. The method of claim 88, wherein formingsaid plurality of gates further includes forming at least one of atransfer gate, a reset gate, and a source follower gate.
 92. The methodof claim 87, further comprising: providing a light-shielding materialover said plurality of gates; and forming openings through saidlight-shielding material, said openings corresponding to and positionedover said plurality of gates.
 93. The method of claim 92, furthercomprising: forming a transparent insulating layer over said pluralityof gates; and forming contact holes within said transparent insulatinglayer, said contact holes corresponding to and positioned over each ofsaid plurality of gates except for said photogate, wherein saidtransparent insulating layer fills the one of said plurality of openingscorresponding to and positioned over said photogate.
 94. A method offorming a pixel cell, comprising: forming a polysilicon layer over asubstrate comprising a doped region; forming a photogate insulator oversaid doped region; forming a metal layer over said photogate insulatorand said polysilicon; forming a silicide from a first portion of saidmetal layer over said polysilicon layer; removing a second portion ofsaid metal layer over said photogate insulator, wherein said removingact comprises retaining said silicide over said polysilicon layer;forming a first gate over said doped region from said polysilicon layer;and forming a second gate from said silicide and said polysilicon layer.